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NJW4800
30V/4A Half Bridge Driver
GENERAL DESCRIPTION The NJW4800 is a general purpose, half bridge power driver capable of supplying 4A current. The internal gate driver drives high-side/low-side power MOSFET; therefore, it has fast switching. Additionally, it has protection features such as over current protection and thermal shutdown. And in the case of failure, it can output a fault flag. It is suitable for power switching applications of DSP/micro controller. PACKAGE OUTLINE
NJW4800GM1
FEATURES Output Switch Current 4A Operating Voltage 7.5V to 30V Up to 1.2MHz Switching Frequency Thermal Shut Down Over Current Protection Under Voltage Lockouts Fault Indicator Output Stand-by Current IQOFF =3A typ. High Heat Radiation Package Package Outline HSOP8
PIN CONFIGURATION
1 2 3 4
8 7 6 5
Exposed PAD on backside connect to GND
PIN FUNCTION 1. PWM 2. VDD 3. OUT 4. GND 5. BS 6. STBY 7. REG 8. FLT
Ver.2010-09-29
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NJW4800
BLOCK DIAGRAM
RFLT FLT REG
CREG VDD
Over current Protection Regulator (5V) Thermal Shut Down
BS
Level Shift
High Side Gate Driver
CBS
Under Voltage Lock Out
OUT PWM
Input Control Low Side Gate Driver 100k
STBY
750k
GND
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Ver.2010-09-29
NJW4800
ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL Supply Voltage V+ VSTBY Input Voltage VPWM FLT pin Voltage VFLT BS pin Voltage VBS BS-OUT pin Voltage VBS-OUT Power Dissipation Operating Junction Temperature Operating Temperature Range Storage Temperature Range PD Tj Topr Tstg (Ta=25C) REMARKS VDD-GND pin STBY, PWM-GND pin FLT-GND pin BS-GND pin BS-OUT pin - - - -
MAXIMUM RATINGS 35 -0.3 6 -0.3 6 40 -0.3 6 900 (*1) 3100 (*2) -40 ~ +150 -40 ~ +85 -50 ~ +150
UNIT V V V V V W C C C
RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL MIN. Operating Voltage Vopr 7.5 Output Switch Current IOM 0 VSTBY, Input Voltage 0 VPWM FLT pin Voltage VFLT 0
TYP. - - - -
MAX. 30 4 5.5 VREG1
UNIT V A V V
(Ta=25C) REMARKS VDD-GND pin OUT pin STBY, PWM-GND pin FLT-GND pin
THERMAL CHARACTERISTICS PARAMETER SYMBOL Junction-toja Ambient Temperature Junction-to-Case jt
THERMAL RESISTANCE 139 (*1) 40 (*2) 19 (*1) 3.7 (*2)
(Ta=25C) UNIT C/W C/W
(*1): Mounted on glass epoxy board based on EIA/JEDEC. (76.2 x 114.3 x 1.6mm: 2-Layers) (*2): Mounted on glass epoxy board based on EIA/JEDEC. (76.2 x 114.3 x 1.6mm: 4-Layers Internal foil area: 74.2 x 74.2mm)
Power Dissipation vs. Ambient Temperature 4 Power Dissipation P (W) 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 o Ambient Temperature Ta ( C)
At on 2 layer PC Board
(Topr=-40~+85oC, Tj= ~150oC)
At on 4 layer PC Board
Ver.2010-09-29
D
-3-
NJW4800
ELECTRICAL CHARACTERISTICS PARAMETER General Characteristics Quiescent Current 1 (Operating) Quiescent Current 2 (Switching) Quiescent Current 3 (Standby) Output Block High-side SW ON Resistance Low-side SW ON Resistance Over Current Limit Output Rise Time Output Fall Time Dead Time PWM Rise Delay Time PWM Fall Delay Time OUT pin - VDD pin Potential Difference GND pin - OUT pin Potential Difference Output Pull-down Resistance Output Leak Current (High Side SW OFF) OUT pin Output Current (FLT Signal Output ) Input Circuit Block STBY pin High Voltage (Standby Mode) STBY pin Low Voltage (Operating Mode) STBY pin Input Current STBY Pull-down Resistance PWM pin High Voltage PWM pin Low Voltage PWM pin Input Current Continuous Output High Time (Unless otherwise noted, V+=12V, VSTBY=0V, CBS=0.1F, CREG=1F, Ta=25C) TEST CONDITION MIN. TYP. MAX. UNIT
SYMBOL
IQ1 IQ2 IQOFF
VPWM=0V VPWM=0V to 3V, fPWM=1.2MHz VSTBY=5.5V, VPWM=0V
- - -
1 9 3
2 14 10
mA mA A
RDSH RDSL ILIMIT tr tf Dt td_ON td_OFF VPDOV VPDGO RPD IOLEAKOUT IO-FLT
IOSOURCE=1A, VBS-OUT=5V IOSINK=1A High-side and Low-side VPWM=0V to 3V VPWM=3V to 0V VPWM=0V to 3V VPWM=0V to 3V VPWM=3V to 0V V+=5.7V, IORH=1A V+=5.7V, IORL=1A V =5.7V, VSTBY=5.5V V+=30V, VSTBY=5.5V, VOUT=0V V+=5.7V, VOUT=0V
+
- - 4 - - - - - - - 50 - -
0.25 0.25 5.5 3 3 20 60 60 0.85 0.85 100 - 30
0.45 0.45 7 - - - - - 1.1 1.1 200 1 60
A ns ns ns ns ns V V k A A
VIHSTBY VILSTBY IISTBY IISTBY VIHPWM VILPWM IIPWM tHPWM VSTBY=5.5V
2.4 0 - 500 2.2 0 - 140
- - 0.01 750 - - 0.01 300
5.5 0.8 1 1000 5.5 0.9 1 -
V V A k V V A s
VPWM=5.5V VPWM=5.5V
Under Voltage Lockout (UVLO) Block UVLO Release Voltage VUVLO2 UVLO Operation Voltage VUVLO1 UVLO Hysteresis Voltage VUVLO
V+ = L H V+ = H L VUVLO2-VUVLO1
5.9 5.65 -
6.6 6.35 0.25
7.3 7.05 -
V V V
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Ver.2010-09-29
NJW4800
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, V+=12V, VSTBY=0V, CBS=0.1F, CREG=1F, Ta=25C) PARAMETER Internal Power Supply Circuit Output Voltage 1 Line Regulation Load Regulation REG pin Output Current Fault Function (FLT pin) Low Level Output Voltage OFF Leak Current SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
VREG1 IREG=0mA VREG-VDD V+=8 30V, IREG=0mA VREG-IO IREG=0 20mA VREG1x0.95, IOREG Input signal=500kHz
4.75 - - 30
5 2 20 -
5.25 20 50 -
V mV mV mA
VLFLT IOLEAKFLT
IFLT=500A VFLT=5.5V
- -
0.25 -
0.5 1
V A
PIN OPERATION TABLE INPUT
OUTPUT Mode High-side Low-side PWM STBY VDD FLT SW SW ON OFF ON Normal L L V+ VRUVLO ON ON (*3) OFF Normal H L V+ VRUVLO L H - OFF OFF OFF Stand-by H H - OFF OFF OFF Stand-by + L L V < VDUVLO OFF OFF OFF UVLO H L V+ < VDUVLO OFF OFF OFF UVLO (*3) If PWM=H continues by tHPWM or more and is input, it becomes low-side SW=ON during tHPWM/128. INPUT Tj Tj >150C - IOUT - IOUT IOM FLT OFF OFF OUTPUT High-side SW OFF OFF
Low-side SW OFF OFF
Mode TSD OCP
Ver.2010-09-29
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NJW4800
TIMING CHART Fig1. Output Rise/Fall Time, PWM Rise/Fall Delay Time
50% PWM
50%
tr 90% 50% OUT 10% td_ON td_OFF 50%
tf 90% 10%
Fig2. Maximum Continuous Output Time (High-level)
PWM tHPWM/128
OUT tHPWM
Fig3. Switching and Dead Time
ON High Side SW OFF ON Low Side SW OFF Dead Time 50ns typ.
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Ver.2010-09-29
NJW4800
TYPICAL APPLICATIONS
V
+
CP=1F
CIN=100F
CREG =1F
RFLT =47k REG
VDD
BS CBS=0.1F
FLT PWM Controller (NJU7600)
FAULT PWM Signal
NJW4800 OUT GND
VOUT
PWM STBY
Stand-by
Synchronous PWM step down switching regulator
V
+
CP=1F
CIN=100F
CREG =1F
RFLT =47k REG
VDD
BS CBS=0.1F
FAULT PWM Signal Stand-by
FLT PWM STBY
NJW4800 OUT GND
Class-D single ended audio amplifier
V
V+ CP=1F CIN=100F
+
CP=1F
CIN=100F
REG
VDD
REG
BS
VDD
BS
FLT
FLT Digital Audio Signal
FAULT PWM Signal
NJW4800 OUT GND
4
PWM STBY
PWM Signal
FAULT PWM Signal
NJW4800 OUT GND
PWM STBY
Stand-by
Stand-by
V+
V
CP=1F CIN=100F
+
CP=1F
CIN=100F
M
REG
VDD
BS
REG
VDD
BS
FLT
FAULT PWM Signal
NJW4800 OUT GND
FLT
FAULT PWM Signal
NJW4800 OUT GND
PWM STBY
PWM STBY
Stand-by
Stand-by
Class-D full bridge audio amplifier
Full bridge motor driver
Ver.2010-09-29
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NJW4800
CHARACTERISTICS
Over Current Limit vs. Temperature 7 (A)
LIMIT
Over Current Limit vs. Temperature 7 (A)
LIMIT
(High-side, V+=12V)
CBS=0.47F CREG=1F
(Low-side, V+=12V)
CBS=0.47F CREG=1F
6.5 6 5.5 5 4.5
6.5 6 5.5 5 4.5
Over Current Limit I
4 -50 -25 0 25 50 75 100 125 150 o Ambient Temperature Ta ( C) High-side SW ON Resistance vs. Temperature (I OSOURCE=1A, VBS-OUT=5V) 0.5 0.4 0.3 0.2 0.1 0 -50 -25
Over Current Limit I
4 -50 -25 0 25 50 75 100 125 150 o Ambient Temperature Ta ( C) Low-side SW ON Resistance vs. Temperature () 0.5 0.4 0.3 0.2 0.1 0 -50 -25 0 25 50 75 100 125 150 o Ambient Temperature Ta ( C) (V+=12V, IOSINK=1A)
DSH
()
High-side SW ON Resistance R
0
25
50
75 100 125 150
o
Ambient Temperature Ta ( C)
Low-side SW ON Resistance R
DSL
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Ver.2010-09-29
NJW4800
CHARACTERISTICS
(s) Continuous Output High Time vs. Temperature 400 380 360 340 320 300 -50 -25 0 25 50 75 100 125 150 o Ambient Temperature Ta ( C) (V+=12V, VPWM=3V)
CREG=1F CBS=0.47F
Internal Power Supply Circuit Load Regulation 5.1
REG1
(V+=12V, Ta=25oC)
CREG=1F
HWM
Continuous Output High Time t
(V) 5 4.9 4.8 Output Voltage 1 V 4.7 0
20 40 60 80 Output Current I REG (mA)
100
Under Voltage Lockout Block vs. Temperature 7.2 7 6.8 6.6 6.4 6.2 6 5.8 -50 -25 0 25 50 75 100 125 150 o Ambient Temperature Ta ( C) PWM pin Voltage vs. Temperature 2 (V)
PWM
STBY pin Voltage vs. Temperature 2 STBY pin Voltage VSTBY (V) 1.8 1.6 1.4 1.2 VILSTBY V
IHSTBY
(V+=12V)
UVLO
(V)
V
UVLO Voltage V
RUVLO
V
DUVLO
1 -50 -25 0 25 50 75 100 125 150 o Ambient Temperature Ta ( C) Frequency vs. Operating Voltage 20 (VPWM=0V to 3V, Ta=25oC)
CBS=0.47F CREG=1F
(V+=12V) (mA)
Q
1.8 1.6 1.4
V
IHPWM
15 10 5
PWM pin Voltage V
Quiescent Current I
V+=30V V+=12V
VILPWM 1.2 1 -50 -25 0 25 50 75 100 125 150 o Ambient Temperature Ta ( C)
V+=7.5V 0 0 200 400 600 800 1000 1200 Frequency fPWM (kHz)
Ver.2010-09-29
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NJW4800
CHARACTERISTICS
Quiescent Current 1 vs. Operating Voltage (mA) 2 1.5 1 0.5 (VPWM=0V, Ta=25oC)
CBS=0.47F CREG=1F
Quiescent Current 1 vs. Temperature 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 o Ambient Temperature Ta ( C)
Quiescent Current 2 vs. Temperature 20 (mA) 15 10 5 0 -50 -25 0 25 50 75 100 125 150 o Ambient Temperature Ta ( C) Quiescent Current 3 vs. Temperature (A) 10 8 6 4 2 0 -50 -25 0 25 50 75 100 125 150 o Ambient Temperature Ta ( C) (V+=12V, V
CBS=0.47F CREG=1F
STBY
(V+=12V, V
CBS=0.47F CREG=1F
PWM
=0V)
Quiescent Current 1 I Q1 (mA)
0
0
5
10
15
20
25
+
30
35
Operating Voltage V (V)
Quiescent Current 2 vs. Operating Voltage Quiescent Current 2 IQ2 (mA) 20 15 10 5 0 (VPWM=0V to 3V, f PWM=1.2MHz, Ta=25oC)
CBS=0.47F CREG=1F
Quiescent Current 1 I
Q1
(V+=12V, V
PWM
=0V to 3V, f
PWM
=1.2MHz)
CBS=0.47F CREG=1F
0
5
10 15 20 25 30 + Operating Voltage V (V)
35
Quiescent Current 3 vs. Operating Voltage Quiescent Current 3 I QOFF (A) 10 8 6 4 2 0 (VSTBY=2V, fPWM=0V, Ta=25oC)
CBS=0.47F CREG=1F
Quiescent Current 2 I
Q2
=2V, V
PWM
=0V)
0
5
10 15 20 25 30 + Operating Voltage V (V)
35
Quiescent Current 3 I
QOFF
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Ver.2010-09-29
NJW4800
PIN DESCRIPTION PIN PIN NAME NUMBER 1 2 3 4 5 6 7 PWM VDD OUT GND BS STBY REG
FUNCTION PWM Signal Input Terminal As for Control Logic, Refer to PIN OPERATION TABLE (page.5) Power Supply Terminal You should connect capacitor (AL and MLCC) for reducing Input Impedance. Output Terminal The High-side/Low-side Switch are Limited to 5.5A(typ.) by Over Current Protection Circuit. Ground Terminal Boot Strap Output Terminal Boot Strap Output drives the High-side Switch. You should connect capacitor larger than 0.1F between BS Terminal (5-pin) and Out Terminal (3-pin). Standby Terminal NJW4800 becomes standby status by High Level NJW4800 operates by Low Level Built-in Regulator (5V) Output Terminal You should connect capacitor larger than 1F for stable output. Fault Signal Output Terminal It is Open Drain Output Type. You should connect through Pull-up Resister to REG Terminal (7-pin) or External Power Supply. It outputs Low Level under normal operating condition and outputs High Level under Abnormal Conditions. Connected to 4pin (Ground Terminal)
8
FLT Exposed PAD
-
Ver.2010-09-29
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NJW4800
FUNCTIONAL EXPLANATION High-side, Low-side Switch The SW output drives the load. It is controlled by the logic input signal from PWM terminal at PWM. When the signal at PWM is high (above 2.2V), the high-side switch is turned on. When the signal at PWM is low (less than 0.9V), the low-side switch is turned on. The NJW4800 uses built-in Nch MOSFETs (RON=0.25 typ.) for both the high-side and low-side switches. The high-side SW gate is driven with V++5V that generated by bootstrap. The high-side SW turn on time is limited to 300sec(typ.). (ex. Fig2) ON There is a dead time region (20nsec (typ.): design value) to High Side prevent short circuit (high-side and low-side) where both the SW high-side and low-side switches are off. (ex. Fig3) OFF The NJW4800 is suitable for high-frequency switching ON regulator. The NJW4800 operates at frequencies up to Low Side 1.2MHz. SW OFF The OUT terminal is pulled down inside with 100k, compensates the leak current of the High-side SW.
Dead Time 20ns typ.
Fig3. SW Function and Dead Time Relation Over Current Protection Function The internal over-current protection circuit monitors the flow currents of both the high-side and low-side switches. The over-current protection circuit operates at 5.5A (typ.) and stops the SW operation. The FLT signal is output from FLT terminal at the same time. The over-current protection operation is released at the PWM input signal falling edge. (ex. Fig4) If OUT terminal is shorted directly to GND, a large surge current is flowing for fast current change and may exceed current limit. Because that time big electric power consumption occurs instantaneously in NJW4800, you should design sufficient heat dissipation. When a load condition is inductive property, a reverse direction current flows to the high-side and low-side SW body diode by inductive kickback. The built-in over-current protection circuit has not aimed at protection against the inductive kickback. Therefore, an external diode should be considered usage against reverse-current regeneration according to the kind of the application.
The Overcurrent Protection is released with the falling edge High Low ON High Side SW OFF ON Low Side SW OFF ON Current Limit OFF Fault Output
(FLT pin Pull-Up)
PWM Input
Hi-Z
Hi-Z
Hi-Z
Hi-Z
High Low
Fig4. Timing Chart of High-side/Low-side Switch at Over Current Protection Operating - 12 Ver.2010-09-29
NJW4800
Boot Strap In order to drive the gate of the high side SW, the voltage that is higher than power supply voltage is necessary. The bootstrap condenser generates the power supply voltage of V++5V to BS terminal and it supplies the power to the gate of the high side SW. As Shown as Fig5 in detail.
V
+
Power Line VDD Regulator Voltage
V
+
Power Line VDD BS Regulator Voltage
V+=5V is generated to the BS terminal.
Regulator 5V High Side Gate Driver
OFF
Regulator 5V
CBS
CBS is charged to 5V
ON High Side Gate Driver
CBS
OUT becomes V+ voltage
OUT
ON Low Side Gate Driver Low Side Gate Driver OFF
OUT
High-side SW: OFF Low-side SW: ON
High-side SW: ON Low-side SW: OFF Fig5. High-side SW driven by Boot Strap
You should connect bootstrap condenser larger than CBS=0.1F between BS Terminal and OUT Terminal. The internal counter decides the bootstrap condenser Charge and Discharge time. A capacitor discharge time (tHPWM) for High-side SW Maximum ON Time is 300ms (typ). A capacitor charge time (tHPWM / 128) for Low-side SW Minimum ON Time is 2.34s (typ). Built-in Regulator The REG Terminal outputs Reference Voltage (5V). It can be used as generating of the voltage for the bootstrap or a power supply voltage for other device(s). You should connect capacitor (CREG) larger than 1F for stable regulator output. This regulator current capability (IOREG) is 30mA (min) at (VREG1 0.95). This regulator over current protection is a drooping characteristic type. It has drooping characteristic at over current protection function. Thermal Shut Down Function When NJW4800 chip temperature exceeds the 170C, internal thermal shutdown circuit operates and SW function is stopped. The Fault signal is output simultaneously from the FLT terminal. In order to return SW operation, you should make chip surface temperature (Junction Temperature: Tj) below the 150C*. This function is a circuit to prevent IC at the high temperature from malfunctioning and is not something that urges positive use. You should make sure to operate inside the junction temperature range rated. (* Design value)
Ver.2010-09-29
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NJW4800
Under Voltage Lockout(UVLO) The UVLO circuit operating is released above V+=6.6V(typ.) and IC operation starts. When power supply voltage is low, because the UVLO circuit operates, IC does not operate. There is 0.25V width hysteresis voltage at rise and decay of power supply voltage. Hysteresis prevents the malfunction at the time of UVLO operating and releasing. FAULT Signal Output This Terminal is Open Drain Output Type. You should connect through Pull-up Resister to REG Terminal (7-pin) or External Power Supply. It outputs Low Level under normal operating condition and outputs High Level under Abnormal Conditions. The following information is output as FAULT signal. Stop Operation at Under Voltage Lockout (UVLO) Over Current Protection Function Thermal Shut Down At the time of standby state, it outputs High Level. When outputting the FAULT signal, it has stopped SW operation, but the internal regulator continues operation. Because of this 30mA it is flowing via the OUT terminal from the regulator circuit. Standby Function NJW4800 stops the operating and becomes standby status when 2.4V or more is supplied to STBY terminal. You should connect the terminal with GND level to prevent the malfunction by a noise when you do not use this function.
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Ver.2010-09-29
NJW4800
APPLICATION TIPS In the application that does a high-speed switching of NJW4800, because the current flow corresponds to the input frequency, the substrate (PCB) layout becomes an important. NJW4800 is driving the High-side/Low-side SW gate with high speed to reduce switching losses. The transient voltage is generated by parasitic inductance and a high-speed current change of high side and low side SW. You should attempt the transition voltage decrease by making a current loop area minimize as much as possible. Therefore, you should make a current flowing line thick and short as much as possible. You should insert a bypass capacitor between VDD terminal and GND terminal to prevent malfunction by generating over voltage and/or exceed maximum input voltage rating. The recommended bypass capacitor is 1F or more high frequency capacitor. A 100F aluminum electrolysis capacitor is recommended for smoothing condenser. However, you should use larger capacitor by sufficient evaluation (assessment) due to load condition and/or application use environment. (There is a possibility that the supply voltage rises by inductive kickback when the supply current of the inductive load is large.) The bypass capacitors should be connected as much as possible near VDD terminal.
Ex. Bill of Materials Components Parts Name CIN CP GRM21BB11H104KA01B CREG GRM31MB31H105KA87B CBS GRM21BR71H474KA88B RFLT RK73B1JT473
Functions Aluminum-Cap. Ceramic-Cap. 0.1F, 50V (B-val) Ceramic-Cap. 1F, 50V (B-val) Ceramic-Cap. 0.1F, 50V (X7R-val) 47k
Manufacturers Nippon Chemi-con Murata Murata Murata KOA
Ver.2010-09-29
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NJW4800 MEMO
[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
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Ver.2010-09-29

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